Abstract: Interpolators are used in digital signal processing systems to increase the sampling rate. An interpolation filter consist of an input matrix and coefficient matrix with up-sampling factor P and filter length N. Interpolation filter has different coefficient vector for different up-sampling factors. Here interpolation filter architecture is designed for different up-sampling factors. Reuse of partial results in reconfigurable filter for eliminating redundancy in computation.Parallel computation is performed by block formulation method. Reconfigurable Interpolation filter is implemented using VHDL language by Xilinx software. A ripple carry adder is used in filter architecture for performing addition operation. A block formulated reconfigurable architecture is presented for area, delay and power efficient realization of interpolation filter.

Keywords: Interpolation, Reconfigurable, VLSI.